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MaksimK30
New Contributor
New ContributorIncorrect PLL simulation in Questasim
Hello, everybody !
I'm new in FPGA and i have a problem with PLL simulation in Questasim.
I'm create clear project, in Platform Designer add ALTPLL core and connect to clock source clk and reset. c0, c1, c2 conducuits is exported.
In questasim i get this plot. Pll generate c0/c1/c2 a little bit and then stop generate signals. Why does it work that way? How i can fix it ? Project attached in the end of post.
Ok, I find my mistake. I incorrect write my testbench module. I should init all registers and add areset and locked wire from PLL
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MaksimK30Ok, I find my mistake. I incorrect write my testbench module. I should init all registers and add areset and locked wire from PLL
