Altera PDN Tool Decoupling Capacitors Results

To whom it may concern,

Would you please provide the schematics of the following refence design:

https://www.intel.com/content/www/us/en/content-details/632722/intel-enpirion-power-solutions-reference-design-for-arria-10.html

The reason for this is that when the VRM models of the Enpirion regulators that are used in the abovementioned reference design are entered into the Altera PDN tool, the PDN tool returns zero decoupling capacitors for the Arria 10 core voltage and a small number of capacitors for the other voltage rails.

We are using high performance voltage regulators in our Arria 10 SX design (with the VRM models entered into the Altera PDN tool), in which the Altera PDN tool produces decoupling capacitors results that are similar to the ones obtained when the VRM models of the Enpirion regulators are used in the tool.

Therefore, would you please provide us with the schematics of the abovementioned reference design so that we get a reassurance.

Is it common that the Arria 10 core voltage only requires a small number of bulk decoupling capacitors (approaching zero) and no small value capacitors when the host PCB is optimized and high performance voltage regulators are employed due to Ftarget and Ztarget of the core voltage? Kindly, advise.

Regards,

F