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Altera_Forum
Honored Contributor
Honored ContributorImplementing CAM (Content Addressable Memory) on Cyclone III
Hi everyone,
I'm new at the Altera Forum and I'm also a newbie in using Altera FPGAs. In order to design a packet filter for a DVB application, I'm looking for a solution to implement a CAM (Content Addressable Memory) on a Cyclone-III FPGA. Can anyone help me with that? Thanks in advance Modellpilot23 Replies
Altera_ForumWhat size do you want? What speeds? Is it Ternary(this is often a deal-breaker for larger CAMs, unless you don't mind using a ton of resources). There's a nice trick for making binary CAMs out of RAMs. I have a parameterized VHDL design for it, but I wrote it a few years ago and it targets either M4Ks or M512s. I can modify it for M9Ks, or might post-it as is for now, but am curious what your requirements are, as it might not work for you.
- Altera_Forum
Sorry, but I think there is a missunderstanding: I'm looking for a CAM not for a RAM :cool:
I allready had a look on Quartus. And Yes, the MegaWizard Plug-In Manager provides a lot of different memory controllers (single/dual-port, single/dual-clock, RAM/ROM/SREG). But CAMs are only supported when using an APEX device. When selecting a Cyclone-III CAMs and Flash Memory is disabled :mad: Modellpilot - Altera_Forum
speak out ur deign spec such as 512x32bit,dual port,dual clock.
In Quartus, it's easy to realize by using megawiard tool!
