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Honored Contributor
Honored ContributorImplementing CAM (Content Addressable Memory) on Cyclone III
Hi everyone, I'm new at the Altera Forum and I'm also a newbie in using Altera FPGAs. In order to design a packet filter for a DVB application, I'm looking for a solution to implement a CA...
Altera_ForumHonored Contributor
Honored Contributorspeak out ur deign spec such as 512x32bit,dual port,dual clock.
In Quartus, it's easy to realize by using megawiard tool!
