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Altera_Forum's avatar
Altera_Forum
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16 years ago

implementing a mux using high impedances

I have many streaming input ports that I want to connect to a single streaming output port.

Rather than using a VHDL case or lengthy ifels statement, I was wondering if I could get tricky with high impedances in order to save some logic resources.

I have attached an example VHDL file showing what I would like to do.

It has 4 streaming input style ports and a single streaming output port.

The first architecture, "typical", implements the standard mux using a case statement, nothing fancy.

The second architecture, "hi_z", implements a mux by using a register for each of the input streams and assigning "Z" to each of the registers except for the one we want to pass through. The register associated with the input stream we wish to be assigned to the output, gets assigned with its associated input.

And the end I have a concurrent assignment of each of the registers to the output stream. The idea is that each of the registers will be set to high impedance, except for the one that I actually wish to pass.

My question is: Will quartus synthesize this logic properly? Will it consume

fewer device resources than the standard mux of architecture "typical"?

thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Did you try with quartus first.

    I have doubts. Remember there is only a tristate buffer at output pins and nothing internal. Any internal Z logic is done in muxes.

    you are first inferring registers applying Z(datain0_d,datain1_d...etc) then you connect all register outputs to one pin. This is not compatible with io structure I believe.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    As said, internal tristate in FPGA can be virtual only. At best, it is converted to multiplexers by the FPGA compiler. I didn't try, if the present code is accepted by Quartus, I've used internal tristate in connecting multiple entities by virtual busses only.

    As a conclusion, internal tristate never saves resources. In my opinion, it doesn't serve a purpose in the present case.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Please read page 6-46 of the coding guidelines:

    http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

    In addition to kaz and FvM's comments, you really should avoid internal tri-states whenever possible. It's truly a luxury for us that the tools even handle them at all. There is no such thing as an internal tri-state in FPGAs. All you are doing is forcing the compiler to figure out a muxing scheme for you and it may not be as efficient as you doing it yourself. And this sort of coding really doesn't fly in the ASIC design world.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I did something similar on an internal level some time back when I did not know better, using Cyclone II. Quartus handles it quite well, but gives a message that it converted the structure using OR gates. As everyone agrees there is no physical structure in the FPGA internal to the FPGA to directly implement the tri-state bus. My example is still in the design and I have no intention of changing it, but I will do it differently next time.