Forum Discussion

Varun_N_C's avatar
Varun_N_C
Icon for New Member rankNew Member
10 hours ago

Implementation of lower data rate.

Hi, I would like to know about implementation of lower data rates (100 - 200Mbps) in cyclone 5 GX and cyclone 10 GX FPGA's. please provide the support by providing the architecture. 

Core Logic
Programmable Logic Device

1 Reply

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 hour ago

    Hi Varun, 
    guess you are asking about operating transceivers at low data rates? Cyclone 10 GX minimal transceivers speed is 1 Gbps, CV GX 614 Mbps. As mentioned in 10 GX transceiver PHY user guide, lower data rates can be achieved by oversampling. The questioned data rates can be implemented directly with LVDS IO, what's the reason to use tranceiver channels?

    Regards
    Frank