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Altera_Forum
Honored Contributor
Honored Contributorimage compression architecture for haar filter
Hello everyone..
Iam new with QuartusII software..i need help from you all..:confused: I was design architecture for image compression using Haar filter and using pipelined technique. As we know, Haar filter consist of 2 algorithm which are averaging and differencing. My question is how suppose i start to write the VHDL code for the architecture? I have problem to evaluate the algorithm into VHDL code because of the - and / operations. I appreciate your helps..6 Replies
Altera_ForumThanks for your respond..i get more clear know.
Thanks for reply- Altera_Forum
then it is quite simple to do arithmatic in VHDL, it is as simple as:
c <= a + b; c <= a - b; c <= a * b; etc. - Altera_Forum
I learn digital logic design during my degree and know i do my master focus in digital design.
I understand to design using gate based on the equation.But know, i need to write VHDL code based on architecture.Hope you understand what i mean. Thank for reply.. - Altera_Forum
Building filters is probably not a great way to start with VHDL. How good are you with digital logic design?
- Altera_Forum
My problem is i dont have any idea to write the VHDL code.
What type of architecture i need to write?..Iam very new with VHDL code.. Thanks for reply.. - Altera_Forum
there is not problems doing subtraction in FPGAs. Divide functions you'll have to instantiate a divide megafunction - quartus cannot pipeline a divide function from infered code yet.
So what problems are you having?
