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Altera_Forum
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15 years ago

image compression architecture for haar filter

Hello everyone.. Iam new with QuartusII software..i need help from you all..:confused: I was design architecture for image compression using Haar filter and using pipelined technique. As we...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

there is not problems doing subtraction in FPGAs. Divide functions you'll have to instantiate a divide megafunction - quartus cannot pipeline a divide function from infered code yet.

So what problems are you having?