Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

image compression architecture for haar filter

Hello everyone.. Iam new with QuartusII software..i need help from you all..:confused: I was design architecture for image compression using Haar filter and using pipelined technique. As we...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

then it is quite simple to do arithmatic in VHDL, it is as simple as:

c <= a + b;

c <= a - b;

c <= a * b;

etc.