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MartinMaa's avatar
MartinMaa
Icon for Occasional Contributor rankOccasional Contributor
14 hours ago

I want to understand the practical difference between Best Speed and Smallest Area in FPGA .

Hello, I currently have an SCFIFO application requirement. The FPGA device I am using is the 10M02SCM153C8G, and I am implementing the FIFO function through an IP core. My application seemed quite si...
Core Logic
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 hours ago

I'm not sure what "the image would occasionally and intermittently split" means as the issue, but is your design meeting timing?  How fast are you running it?

Like it says there, best speed is inserting an additional register.  Are you taking into account this extra cycle of latency elsewhere in your design?