Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I can't solve the wrong with a stop watch desiging

I was designing a stop watch this week,but get some troubles.

There are four keys---reset,stop,minset(minute set),and secset(second set) in the watch.The reset and stop fuctions are right,but the minset and the secset won't make the minute or the second +1 successfully,and show some error numbers.I don't know why.

This is my code:

module SECLOCK(clk,sclk,rundir,key);

input clk,sclk;//clk--system clk,sclk---percentage second

input rundir;//run direction

input[3:0] key;// 4 keys

reg[32:0] j;//the total percentage seconds,to generate min,sec,percentage second

reg run;//stop mark

reg keyclk;

reg ssclk;

always @(posedge clk)//scan the keys' value,when key!=0,keyclk set high

begin

if(key!=0) keyclk<=1;

else keyclk<=0;

end

always @(sclk)//avoid the conflict between keyclk and ssclk

begin

if(keyclk!=0) ssclk=0;

else ssclk=sclk;

end

always @(posedge keyclk or posedge ssclk)

begin

if(keyclk)

begin

case(key0)

4'b0001://reset

begin

j<=0;

run<=0;

end

4'b0010://stop

begin

run<=~run;

end

4'b0100://set second + 1

begin

j<=j+33'd100;

end

4'b1000://set min + 1

begin

j<=j+33'd6000;

end

endcase

end

else

begin

if(run==1 && rundir==1 ) //forward count

j<=j+1;

else if(run==1 && rundir==0 && j>0) //reward count

j<=j-1;

end

end

endmodule

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    An edge sensitive always block must have only one input clock exclusively.

    Generally, you should tell about the reported errors.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    No errors,the report shows.

    I use the signaltap 2 to monitor the signals' changes.the control signal's chang is correct,but the “j” changed not rightly.

    If using one input clock exclusively ,how should I modify my code?

    I would give more detail information tomorrow.

    The signaltap show ,the error is focused on “ssclk”.

    I divided the keyclk fuction and ssclk fuction. The project ran normally. When the keyclk have a posedge edge ,”j” add 6000 or 100 correctly.

    When I get them together ,the wrong appeared. It seemed that I hadn’t hold the ssclk signal low during during the keyclk hold high.

    The key error is here ,I think:

    always @(sclk)//avoid the conflict between keyclk and ssclk

    begin

    if(keyclk!=0) ssclk=0;

    else ssclk=sclk;

    end

    but why?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    In Quartus synthesis, the said always@(sclk) block works as a simple conditional assignment:

    assign ssclk=(keyclk)?0:sclk;

    But keyclk must be added to the sensitivity list to get the same result in other tools, too. I don't understand the purpose of the operation, however.

    Regarding the always @(posedge keyclk or posedge ssclk) block, my first comment wasn't exact. keyclk is an asynchronous reset, in so far it's legal. But you can't have expressions like j<=j+33'd100; in the asynchronous reset part, because you can't build a counter from latches.

    I fear, you're missing a clear concept of the overall design.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    four keys(posedge keyclk touch off):

    (1)reset:j=0,run=0;

    (2)stop:run=~run;

    (3)sec:j=j+100;

    (4)min:j=j+6000;

    sclk:50MHz(clk)->100HZ(sclk)

    1% second count(posedge sclk touch off): j=j+1;---->ssclk touch off(avoid conflict between keyclk or ssclk)

    I add the keyclk to the sensitivity list later(Sorry,I didn't know that error before),but have not any change.

    I can't understand the sentence of"you can't build a counter from latches".

    Can you explain it for detail.

    I give a .doc file,to show a successful case.If you need the project,I will send it.

    If the overall design is wrong ,how should I do it.I really have not any ideas now.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I get it!

    I used one trigger source to replace the old sources,and get successed.

    So interesting the end is.

    But I really want to know why my old codes excute exceptionally. I use the signaltap to monitor the signal,and the result is out of logic.

    Fvm,Thanks for your help.