I can't solve the wrong with a stop watch desiging

In Quartus synthesis, the said always@(sclk) block works as a simple conditional assignment:

assign ssclk=(keyclk)?0:sclk;

But keyclk must be added to the sensitivity list to get the same result in other tools, too. I don't understand the purpose of the operation, however.

Regarding the always @(posedge keyclk or posedge ssclk) block, my first comment wasn't exact. keyclk is an asynchronous reset, in so far it's legal. But you can't have expressions like j<=j+33'd100; in the asynchronous reset part, because you can't build a counter from latches.

I fear, you're missing a clear concept of the overall design.