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Altera_Forum
Honored Contributor
15 years agoNo errors,the report shows.
I use the signaltap 2 to monitor the signals' changes.the control signal's chang is correct,but the “j” changed not rightly. If using one input clock exclusively ,how should I modify my code? I would give more detail information tomorrow. The signaltap show ,the error is focused on “ssclk”. I divided the keyclk fuction and ssclk fuction. The project ran normally. When the keyclk have a posedge edge ,”j” add 6000 or 100 correctly. When I get them together ,the wrong appeared. It seemed that I hadn’t hold the ssclk signal low during during the keyclk hold high. The key error is here ,I think: always @(sclk)//avoid the conflict between keyclk and ssclk begin if(keyclk!=0) ssclk=0; else ssclk=sclk; end but why?