HPS - FPGA used inside block diagram file.

Sirs, I'm starting using Quartus II and a DE1-SOC board (CYCLONE V). I designed a peripheral in Quartus II using a block diagram file as the main file (.BFD), and several Verilog components. The peripheral works fine and now I need to export 8 32 bit registers to the HPS. I created in QSYS a module with the HPS, configured it and generated the HDL, the resulting symbol file was created and I was able to import it to the block diagram. The problem is that the system will never compile unless the HPS is the top level entity... I tried then building an example system only using QSYS and it works that way, but I cannot easily implement the whole system just using QSYS. So the question is, "is it possible to create a system with the verilog libraries and a block diagram, and later incorporate a module of the HPS to export the resulting data?". The information out there is really confusing about this.