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Honored Contributor
Honored ContributorHPS - FPGA used inside block diagram file.
Sirs, I'm starting using Quartus II and a DE1-SOC board (CYCLONE V). I designed a peripheral in Quartus II using a block diagram file as the main file (.BFD), and several Verilog components. The peri...
Altera_ForumHonored Contributor
Honored ContributorWell, just to share my experience, I managed to re-write the connections in the BFD diagram into a verilog .v structured file, and everything worked. The only thing is that you need to export the memory signals to the top of the .v module, and run the tcl memory script, such as it was explained in some tutorials. I did the same with the BDF block diagram, with no success...
