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Well, just to share my experience, I managed to re-write the connections in the BFD diagram into a verilog .v structured file, and everything worked. The only thing is that you need to export the memory signals to the top of the .v module, and run the tcl memory script, such as it was explained in some tutorials. I did the same with the BDF block diagram, with no success...
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Sadly I have the same problem.
I haven't found any solution for this problem until now.
It would be very good to have the chance to include the HPS as a block symbol, so it will be possible to get a better overview about the system.
Honored Contributor
