HPS - FPGA used inside block diagram file.

I managed to rebuild the connections of the bsf system by hand using structural verilog and using that as a top file (such as the examples in: http://zhehaomao.com/blog/fpga/2013/12/22/sockit-1.html) and it worked fine. I just cant understand why building it graphically doesn't work. It looks like it have something to do with the exported signals from the "memory" interface, I tried several combinations of assigning them with no sucess.