HPCII ddr2 controller

The ready signal must be high during that cycle otherwise it won't work.

Thats right. I do have the burst_begin and the local_read_req high for 1 clock cycle when the mem_local_ready is high. But I dont see any activity from the altmemphy.

You need to have read_request and burst_start high to start a reading cycle for one cycle. I usally wait one cycle bfore applying the next request, since two data words are read out, but that's not requiered.

when do_read0 =>
   if (command = c_command_READ and addr_empty = '0') then
       read_req   <= '1';
       burstbegin <= '1';
       if (ready = '1') then
           state <= do_read1;
       end if;
    else
       state <= idle;
    end if;
when do_read1 =>
   if (ready = '1') then
       state <= do_read0;
    end if;

Thank you. writes happen fine now. I am trying to issue a read transaction by setting the local_read_req high for 1 clock along wiht the size and the address. I dont see the afi_cs_n changed from f at all, indicating that the altmemphy is not forwarding the read transaction requested on the avalon interface. Any clues ??

You have to keep the write_req hight for the size of the transfer. The burst start must stay high only for the first cycle.

Thanks. That works. Incase of HPCII DDRII controller wiht local interface, for a half-rate write transaction, do I have to keep the write_req signal high just for one clock cycle when the mem_local_ready is asserted, or do I have to assert write_req for the number of clocks equal to the size of the transfer. I document does not describe this clearly.

Try to generate your model with skip calibration option (only for simulation), that way it should be finished in less than 50 us.