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Altera_Forum's avatar
Altera_Forum
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15 years ago

HPCII ddr2 controller

Hi, I generated HPCII ddr2 controller using megawizard. I included the module in my fpga design and trying to run simulation. I dont see the local_init_done signal going high at all. As per the do...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You have to keep the write_req hight for the size of the transfer. The burst start must stay high only for the first cycle.

Also you need to check if the ready signal is high when initialising a burst.

Look at the timing diagramm in the UG of the DDR HP Ctrl.