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Altera_Forum's avatar
Altera_Forum
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15 years ago

HPCII ddr2 controller

Hi, I generated HPCII ddr2 controller using megawizard. I included the module in my fpga design and trying to run simulation. I dont see the local_init_done signal going high at all. As per the do...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You need to have read_request and burst_start high to start a reading cycle for one cycle. I usally wait one cycle bfore applying the next request, since two data words are read out, but that's not requiered.

Also ready needs to be high.

Check the timing diagramm. 


when do_read0 =>
   if (command = c_command_READ and addr_empty = '0') then
       read_req   <= '1';
       burstbegin <= '1';
       if (ready = '1') then
           state <= do_read1;
       end if;
    else
       state <= idle;
    end if;
when do_read1 =>
   if (ready = '1') then
       state <= do_read0;
    end if;