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Honored Contributor
Honored ContributorHPCII ddr2 controller
Hi, I generated HPCII ddr2 controller using megawizard. I included the module in my fpga design and trying to run simulation. I dont see the local_init_done signal going high at all. As per the do...
Altera_ForumHonored Contributor
Honored ContributorThanks. That works. Incase of HPCII DDRII controller wiht local interface, for a half-rate write transaction, do I have to keep the write_req signal high just for one clock cycle when the mem_local_ready is asserted, or do I have to assert write_req for the number of clocks equal to the size of the transfer. I document does not describe this clearly.
