How to write data into DDR3 SDRAM-HPS!

According to your post, it seems that your Frame Reader has access to the entire HPS address space. If you are using a Cyclone V SOC, the HPS SDRAM address starts at 0x0010_0000 and ends at 0xC000_0000

Try writing to 0x0010_0000 and see whether that works :)

Hi WH2011

Thank you for your reply.

As your comment, the HPS SDRAM address starts at 0x0010_0000 and ends at 0xC000_0000. Because, I don't find the material that mention this feature, Do you give me the related material.

Thank you!

I am looking forward your reply!

https://www.alteraforum.com/forum/attachment.php?attachmentid=9331

The above shows the memory mapping of the FPGA into the ARM. Your FPGA has access to the physical address of the HPS SDRAM starting from 0x10_0000. Note however that the Qsys Avalon address bus to the HPS SDRAM port is only 29 bits wide instead of 32 bits. Thus, you can only access memory up to address 0xa000_0000 from the FPGA.

I recommend you look at the Macnica online video http://www.macnica-na.com/vworkshops/courses-altera-soc for a great tutorial on this subject.

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https://www.alteraforum.com/forum/attachment.php?attachmentid=9331

The above shows the memory mapping of the FPGA into the ARM. Your FPGA has access to the physical address of the HPS SDRAM starting from 0x10_0000. Note however that the Qsys Avalon address bus to the HPS SDRAM port is only 29 bits wide instead of 32 bits. Thus, you can only access memory up to address 0xa000_0000 from the FPGA.

I recommend you look at the Macnica online video http://www.macnica-na.com/vworkshops/courses-altera-soc for a great tutorial on this subject.

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Hi WH2011!

Thank you so much for introducing the great website like this. It's very useful for me

I would like to share something about my project with you:Firstly, I use a camera TRDB D5M of altera, the picture from camera will be stored at DDR3-FPGA, then displaying VGA. My result is good, Attached image below is my design system in Qsys.

Now, I would like to use HPS in my design. I intend to read data from DDR3-FPGA to save DDR3-HPS, then Frame Reader will be read this data and output to VGA.

How do you think about my ideal, if it is possible or not.

Best Regards!https://www.alteraforum.com/forum/attachment.php?attachmentid=9332

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It is definitely possible. However, you need to use the HPS-FPGA axi bus and not the lightweight axi bus for higher data throughput.

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Hi WH2011!

I think I will use 3 bridges:

+ Lightweight axi: this only use to control Frame Reader

+ HPS-FPGA Bridge: I will use this bridge to read data from DDR3-FPGA to save to DDR3-HPS

+ FPGA-HPS Bridge: Frame Reader will be connected with this bridge to read data from DDR3-HPS and output to VGA

Now, I am doing this project, but I have a problem when using arm to read data from DDR3-FPGA and Frame Reader read data from DDR3-HPS and output to VGA.

Do you give me a direction for me

Sorry if I disturb you!

BR,

I can't help you if you don't tell me the specifics of the problem you're facing. Are you using Linux for your HPS? I can give you some general tips though:

1. The HPS SDRAM ports must be configured to an Avalon bus. I tried AXI but it does not work.

2. If you're using Linux, the preloader must be regenerated everytime you modify the HPS Qsys component

3. Use the following steps to initiate the HPS-FPGA HPS SDRAM interface properly if using Linux:

-Cold boot HPS

-Load FPGA image

-Warm boot HPS

Hi ,

i want to write data which is come from ethernet(connected with fpga) to hps-sdram. And then i have to read the hps-sdram and send out by serial using rs422.

i don't have any knowledge about HPS. tell me some suggestion.