How to turn off all output port of MAXII during power-on.

--- Quote Start ---

As MAXII datasheet at page 4-7 says, IO ports should be at Tri-state. However, It does not seem that my circuit works like that.

--- Quote End ---

The MAX II devices work per their data sheet.

Please check the following:

1) Have you ensured that your reset logic is correct? For example, is it synchronized to the clocks within the design?

2) What have you done with unused pins? Do you have extra I/O wired on the board to MAX II pins that your HDL design is not currently using? There are settings in Quartus that can default to driving the unused signals to ground. If you have accidentally selected this setting, and you have external signals driving those pins on the MAX II, then you can damage the device.

3) Have you checked whether you are violating the MAX II I/O voltage limits? For example, the MAX II devices are not 5V tolerant.

Post your schematic if you can. People on this list will review it.

Cheers,

Dave

Thank you for reply..

I am using more than one CPLD, and these chips are connected each other. When these CPLDs are powered on, some signals (a pulse) occur at the first 200us (SRAM downloading time). I think, at this time, some collision may happen.

1. This signal occur for a combinational logic in my design, which do not need reset logic.

2. In Quartus Program, I set input tri-state as unused pins.

3. I only use 3.3v.

--- Quote Start ---

I am using more than one CPLD, and these chips are connected each other. When these CPLDs are powered on, some signals (a pulse) occur at the first 200us (SRAM downloading time). I think, at this time, some collision may happen.

1. This signal occur for a combinational logic in my design, which do not need reset logic.

2. In Quartus Program, I set input tri-state as unused pins.

3. I only use 3.3v.

--- Quote End ---

Each MAX II CPLD will *not* generate a signal while it is configuring. What you are describing sounds like it is coming from *your* CPLD logic.

Do you have a common reset that routes to all of these designs?

You should have a common reset that is deasserted once all of the devices are configured and the clocks are stable.

Cheers,

Dave

As clearly documented in the device manual, MAX II I/O-pins are configured as input with weak pull-up during power up. Presumed the specification is correct, you'll see a positive pulse generated by the pull-up resistors during power-on reset. It's basically the same state that you'll observe for an unconfigured device.

If the assumption is right, there are two points to mention.

- There's absolutely no problem of collision involved with weak pull-up resistors.

- Weak pull-ups may be still a problem with active high output pins that are activating some function unintentionally. In this case you should either change the logic to active low or place external pull-down resistors overriding the weak pull-ups, e.g. 1k.

Regards,

Frank