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I am using more than one CPLD, and these chips are connected each other. When these CPLDs are powered on, some signals (a pulse) occur at the first 200us (SRAM downloading time). I think, at this time, some collision may happen.
1. This signal occur for a combinational logic in my design, which do not need reset logic.
2. In Quartus Program, I set input tri-state as unused pins.
3. I only use 3.3v.
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Each MAX II CPLD will *not* generate a signal while it is configuring. What you are describing sounds like it is coming from *your* CPLD logic.
Do you have a common reset that routes to all of these designs?
You should have a common reset that is deasserted once all of the devices are configured and the clocks are stable.
Cheers,
Dave
Honored Contributor
