How to turn off all output port of MAXII during power-on.

Thank you for reply..

I am using more than one CPLD, and these chips are connected each other. When these CPLDs are powered on, some signals (a pulse) occur at the first 200us (SRAM downloading time). I think, at this time, some collision may happen.

1. This signal occur for a combinational logic in my design, which do not need reset logic.

2. In Quartus Program, I set input tri-state as unused pins.

3. I only use 3.3v.