Honored ContributorHi,
Because the FPGA development board is installed on a remote machine, I have no access to the physical buttons on board, is there any other way to raise the reset signal after downloading the configuration code? Or is the reset signal raised automatically every time a new configuration code is downloaded? Thanks
Honored ContributorWhat's the configuration interface to the FPGA?
Honored ContributorHonored ContributorI presume you are talking about JTAG indirect programming of AS or AP configuration memory?
"Initiate configuration after programming" is an option that can be either checked or unchecked in the programmer tool. The initiate through JTAG is equivalent to asserting nConfig in hardware.Honored ContributorHonored ContributorI presonnaly add in my vhdl code a ram of 1 bit that is pre-loaded with the value 1.
A little process checks if the value is 1 (so after programming or power cycling from the epcs128), if the value is 1, I assert the internal reset of my design and clear the bit in the ram.Honored ContributorI realize that the original question is somewhat vague. Generally, the power-on-reset will be triggered after configuration, setting internal RAM and registers to there programmed initial state. If your design uses an explicite asynchronous reset signal, the power-on-reset state of registers will be usually identical to the state programmed for the asynchronous reset. In so far, the you get almost the same state by POR without asserting the external reset signal.
A problem arises with those design parts that require the reset released synchronously with the clock, e.g. state machines or counters that are at risk to fall into illegal states otherwise. In this case a particular self-reset may be necessary. To reduce the risk of metastable states, it's often implemented as a down counter that releases the global reset after several clock cycles. If the global clock is fed by a PLL, the reset may be derived from it's locked signal.
