How to trigger the Reset signal

I realize that the original question is somewhat vague. Generally, the power-on-reset will be triggered after configuration, setting internal RAM and registers to there programmed initial state. If your design uses an explicite asynchronous reset signal, the power-on-reset state of registers will be usually identical to the state programmed for the asynchronous reset. In so far, the you get almost the same state by POR without asserting the external reset signal.

A problem arises with those design parts that require the reset released synchronously with the clock, e.g. state machines or counters that are at risk to fall into illegal states otherwise. In this case a particular self-reset may be necessary. To reduce the risk of metastable states, it's often implemented as a down counter that releases the global reset after several clock cycles. If the global clock is fed by a PLL, the reset may be derived from it's locked signal.