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Altera_Forum
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13 years ago

How to trigger the Reset signal

Hi, Because the FPGA development board is installed on a remote machine, I have no access to the physical buttons on board, is there any other way to raise the reset signal after downloading th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I presonnaly add in my vhdl code a ram of 1 bit that is pre-loaded with the value 1.

A little process checks if the value is 1 (so after programming or power cycling from the epcs128),

if the value is 1, I assert the internal reset of my design and clear the bit in the ram.