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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

How to synchronize the inputs of multiple ADC chips using the JESD204B IP core in an FPGA?

Hello everyone, I have encountered some issues in designing an FPGA solution for receiving ADC data. The FPGA I am using is stratix10-1SX110HN2F43I2VG, which has two tiles, with each tile hav...
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  • allen18's avatar
    allen18
    2 years ago

    I have solved this problem. I used a clock buffer chip to replicate multiple sets of clocks.

ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Allen,

Thank you for reaching out.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZulsyafiqH_Intel