How to synchronize divided PLL outputs?

I'm working on a system with multiple Stratix III devices on it. There is a master clock feeding each one, say 10ns period, and each FPGA creates some divided down clocks(all powers of 2). The problem is that I don't have any control on if the divided down clocks are edge-aligned across FPGAs.

For example, the input clock has rising edges at 0, 10, 20, etc. If multiple FPGA's create a divide by 8 clock with a PLL, one may have edges at 0, 80, 160..., another at 20, 100, 180, ... and another at 40, 120, 200,... Is there a way to synchronize these? I basically want to release the divide down output counters after the PLL has locked.

The areset pin resets the VCO, so it moves back to far. It might be possible with the SIII dynamic phase shifting, but that seems like a lot of work. It could definitely be done by just using the 1x clock and creating a system wide clock enable for each lower frequency, but that requires recoding a lot of logic(and if I use IP that doesn't have a system-wide clock enable, it won't work).

Anyway, wondering if anyone else has encountere this?