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Honored Contributor
Honored ContributorHow to synchronize divided PLL outputs?
I'm working on a system with multiple Stratix III devices on it. There is a master clock feeding each one, say 10ns period, and each FPGA creates some divided down clocks(all powers of 2). The pro...
Altera_ForumHonored Contributor
Honored ContributorI hadn't considered using the ALTCLKCTRL megafunction with enables instead of the PLL dividers - thanks for pointing it out. I like it - into the bag'o'tricks it goes.
