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Altera_Forum
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18 years ago

How to synchronize divided PLL outputs?

I'm working on a system with multiple Stratix III devices on it. There is a master clock feeding each one, say 10ns period, and each FPGA creates some divided down clocks(all powers of 2). The pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello Rysc,

don't know if the question is still pending? I think, the most simple solution for synchronizing derived clocks between indepent PLLs is to distribute the slowest rather than the fastests clock. Consider a PLLs having /2, /4.. /16 divided outputs. If the /16 clock phase matches, all other also do. Don't know if this solution applicable for your design. I have e. g. a distributed system with different communication channels: a 20 MHz SPI and multichannel 400 MHz LVDS. All clocks are derived from a 20 MHz clock distributed by master FPGA.

Regards,

Frank