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Honored Contributor
Honored ContributorHow to synchronize divided PLL outputs?
I'm working on a system with multiple Stratix III devices on it. There is a master clock feeding each one, say 10ns period, and each FPGA creates some divided down clocks(all powers of 2). The pro...
Altera_ForumHonored Contributor
Honored ContributorI have met this problem in my work too. Fortunately, the frequency in my design is lower than K ,so I don't have to care much about the synchronizing.
What we met is really a problem, is there some better ways except the DPA ? Hope so.
