How to square a fixed point number?

a <= b * c;

will pretty much always infer a DSP block. The amount of pipelining is determined by you - by how many registers you place around the multiplier in your code. the multiplier above can be placed inside or outside a synchronous process. No VHDL function is pipelined.

You can map the sfixed to std_logic_vector and back again with:

signal port_input, port_output : std_logic_vector(7 downto 0);
signal my_sfixed, sfixed_op  : sfixed(3 downto -4);
.....
port_input <= to_slv(my_sfixed);
sfixed_op <= to_sfixed(port_output, sfixed_op'high, sfixed_op.low);

You need to design the multiplier to be correct. But the fixed_pkg is purely a way to represent an integer in your code. It makes no difference to the underlying hardware

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a <= b * c;

will pretty much always infer a DSP block. The amount of pipelining is determined by you - by how many registers you place around the multiplier in your code. the multiplier above can be placed inside or outside a synchronous process. No VHDL function is pipelined.

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That pipelining is going to be external to multiplier. With inference you can not decide internal pipe which could fail timing

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That pipelining is going to be external to multiplier. With inference you can not decide internal pipe which could fail timing

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You have to let the synthesizer/fitter do register retiming, and the synthesisor WILL infer internal pipe stages.

There is a bug for stratix 4 that means that for larger multipliers (larger than 18x18, so multiple DSPs required) the output register is not inferred properly, and so an LPM mult block is required to use all the internal pipe stages, but the same bug is not present on Stratix V or Arria 10.

This was an issue I came up against and confirmed it with Altera support.