How to square a fixed point number?

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a <= b * c;

will pretty much always infer a DSP block. The amount of pipelining is determined by you - by how many registers you place around the multiplier in your code. the multiplier above can be placed inside or outside a synchronous process. No VHDL function is pipelined.

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That pipelining is going to be external to multiplier. With inference you can not decide internal pipe which could fail timing