How to square a fixed point number?

a <= b * c;

will pretty much always infer a DSP block. The amount of pipelining is determined by you - by how many registers you place around the multiplier in your code. the multiplier above can be placed inside or outside a synchronous process. No VHDL function is pipelined.

You can map the sfixed to std_logic_vector and back again with:

signal port_input, port_output : std_logic_vector(7 downto 0);
signal my_sfixed, sfixed_op  : sfixed(3 downto -4);
.....
port_input <= to_slv(my_sfixed);
sfixed_op <= to_sfixed(port_output, sfixed_op'high, sfixed_op.low);

You need to design the multiplier to be correct. But the fixed_pkg is purely a way to represent an integer in your code. It makes no difference to the underlying hardware