How to simulate the FPGA neural network in Altera

So what I should do with my continous time integrator block with simulink? AMybe just to change to Discrete time? Or I need to add some clock to such integrator or just change the block?

I also found the Filter HDL Coder in Matlab 2009 -- what is the abilities of such programm--can I generate and simulate HDL code, or just generate?

I also read about VHDL and VErilog in HDL coder -- why you talk about just of VHDL?

First express your integrator in discrete domain (z-domain). Yes you have to use discrete time. You need to set up the fixed time step as well.

It seems that you really want to use HDL coder. That is fine. In HDL coder you can generate code and simulate your design. However, you will not be able to verify that your model has been accurately converted to HDL.

You will need to simulate your HDL in Modelsim or ActiveHDL to validate the conversion. (This is not trivial to do).

I thought HDL coder can only make VHDL code, but if it can make Verilog code then go for it. DSP builder can only make VHDL. Either way, the code will probably be difficult to analyze by hand since the conversion process will generate very non-descriptive register name. It is not easy to read through the generated HDL code.

But to start, first you need to make a continuous simulink model and verify its functionality. Then post it here and I can tell you what to do next.

So can I generate the HDL just with Filter Design Coder from Matlab2009 -- I have now--it seems generate, and verify on HDL testbench but in Model-Sim.

Here is my continious time model-- it could be change to discret time--but the results is just simple line and also vertical line so something incorrect, so i left continous time--http://s000.tinyupload.com/?file_id=18188888348335316509

OK i see what is going on. When you do discrete functions you need to set up the proper fixed time step. If the time step is too large, you will not get the right results. I set the time step to less than 0.001 (i like 0.0001 better, the is 10kHz) and my discrete results match the continuous results. Fixed time step is set in Simulation > Configuration Parameters.

I am attaching my discrete model. You are using Matlab 6.5 correct? I am attaching a 2009a version and a 6.5 version. I use 2013b so i have to back convert. Hopefully one of these files works for you.

My Simulink 5.0 tells me that your MAtlab 6.5 version is newer then mine -- 6.5.0.18091 (R13). Where I should note 0.001 -- in Max, Min, Initial Step in Simulation Parameters? I thought early iy should be in Sample Time as by default it seems to be 1 (inherited --> -1). But it doesnot work now.

But I located my Mdl file to convert it to VHDL and test it .. in DSP, ModelSim, SystemGenerator

Ok you definitely need to upgrade matlab. Also in the simulation configuration panel, you are probably still using "Variable Step". You can change that to "Fixed Step" then use 0.001.

Sample Time is in "seconds". So Sample time of 1 = 1 second per step. Sample Time of 0.001 is 1/1000 of second per step. Sample Time of -1 mean use the same sample time as the block before or as set in the configurations.

Yeah your simulimk/matlab is so old that I can't even back convert it that far.

Yes I applied fixed-time step yet to Discrete time integrator and nothing changes . I see 3 lines horizontally, and several blue lines vertically.

Anyway you can simulate HDL with my example and show me the results?

And I have not installed MAtlab2009 with Filter design HDL coder -- could I use this for generation HDL and then to simulate on Model Sim?

Yes I opened you discrete integrator that works fine but in Matlab2009.

I do not know why it is not works with Matlab 6.5 So How can I wright the path to MAtlab 6.5 or 7.8 portable in DSP Blockset. Except the discrete time parameters it needs also additional parameters in Simulation settings for farther HDL generation in DSP.

Anyway --why you could not launch the blocksystem with generated HDL code in MODel iM to allow me to view the results in Altera. As I have generated Verilog code in Fileter Design Coder but after automatic launch of this file in ModelSim the app hanged up. And you said the code is to generic or so. Anyway what I could get when see the HDL simulation-- what is rationale of this rectangle signals -- should they resemble my display of signals like in Scope block in Simulink?

I don't fully understand what you are saying here.

But here is what I gather:

1) The discrete sinmulink44_d2009a.mdl file working in Matlab 2009. This is good.

2) You some how generated HDL from this design? Not sure if this is what you are saying.

But in my opinion you should NOT have been able to do this. This is because although the design is discrete (set sample time), it is NOT DIGITAL (values/amplitudes being fixed point). Think for an ADC (analog to digital converter). It's job is to convert continuous real world values in to digital signals. So if you have an 8 bit ADC, it can only create 256 values (2^8), so your real world signal will be binned into one of the 256 possible outcomes.

The fixed point toolbox in matlab can help you with that. In the simulink design you have to specify your "output data type". You can do this individually for all constants and arithmetic blocks by double - clicking them, then going to "signal attributes" tabs and then under "output data type" selecting fixdt(a,b,c). a is signed (1) or unsigned (0). b is total bit length, c is fractional length. So if you use fixdt (1, 4, 2) this means you will have 4 bits - 1 is for the sign, 2 are for the fraction. If you click the ">>" box you can get details about your allowable range using these parameters. So fixdt(1,4,2) will allow to have ranges from -2 to 1.75 with a digital step of 0.25 (1/2 ^ 2). Think of it as 4 spaces where the first one is the sign, second one is the integer and the last two are you decimal place in the power of 2: (sign) _ . _ _

What is important to note is what values you can be getting especially when you multiply. For example if you were to multiply two fixdt(1,4,2) numbers together, your output will no longer be in the -2 to 1.75 range. It will be in the -3.5 to 4 range. There for you will need to adjust your output data type. Normally you can just add the number data types together: so you will get fixdt(1, 4+4, 2+2) = fixdt(1,8,4). In DSP builder can take care of that better and simulink on its own does.

Once you do that and verify that that works, then you can proceed with generating HDL. Not trivial, right? It is not easy going from continuous to digital domain (time and values are discrete), but it is possible.

So i am attaching the digital version of your design (discrete in time and in values). For constants I used fixdt(1,12,6) and for multiplication i used fixdt(1,24,12). This is probably too much range, but you can adjust as you like. Let me know if it works for you. Remember you MUST have the Fixed Point Toolbox!