How to simulate the FPGA neural network in Altera

I don't fully understand what you are saying here.

But here is what I gather:

1) The discrete sinmulink44_d2009a.mdl file working in Matlab 2009. This is good.

2) You some how generated HDL from this design? Not sure if this is what you are saying.

But in my opinion you should NOT have been able to do this. This is because although the design is discrete (set sample time), it is NOT DIGITAL (values/amplitudes being fixed point). Think for an ADC (analog to digital converter). It's job is to convert continuous real world values in to digital signals. So if you have an 8 bit ADC, it can only create 256 values (2^8), so your real world signal will be binned into one of the 256 possible outcomes.

The fixed point toolbox in matlab can help you with that. In the simulink design you have to specify your "output data type". You can do this individually for all constants and arithmetic blocks by double - clicking them, then going to "signal attributes" tabs and then under "output data type" selecting fixdt(a,b,c). a is signed (1) or unsigned (0). b is total bit length, c is fractional length. So if you use fixdt (1, 4, 2) this means you will have 4 bits - 1 is for the sign, 2 are for the fraction. If you click the ">>" box you can get details about your allowable range using these parameters. So fixdt(1,4,2) will allow to have ranges from -2 to 1.75 with a digital step of 0.25 (1/2 ^ 2). Think of it as 4 spaces where the first one is the sign, second one is the integer and the last two are you decimal place in the power of 2: (sign) _ . _ _

What is important to note is what values you can be getting especially when you multiply. For example if you were to multiply two fixdt(1,4,2) numbers together, your output will no longer be in the -2 to 1.75 range. It will be in the -3.5 to 4 range. There for you will need to adjust your output data type. Normally you can just add the number data types together: so you will get fixdt(1, 4+4, 2+2) = fixdt(1,8,4). In DSP builder can take care of that better and simulink on its own does.

Once you do that and verify that that works, then you can proceed with generating HDL. Not trivial, right? It is not easy going from continuous to digital domain (time and values are discrete), but it is possible.

So i am attaching the digital version of your design (discrete in time and in values). For constants I used fixdt(1,12,6) and for multiplication i used fixdt(1,24,12). This is probably too much range, but you can adjust as you like. Let me know if it works for you. Remember you MUST have the Fixed Point Toolbox!