XQSHEN
Occasional Contributor
Occasional Contributorhow to set timing constraints for source synchronous inputs
based on AN433 page 43~44.
Question 1:
We define both virtual clock and input clock here.
I think input clock is enough for timing constraint.
Why need both?
Question 2:
We define both input clock and generated clock after pll.
Then we which one should be used for define set_input_delay for data_in?
