How to set multicycle for this design?

Try to put your signal names between "".

TCL syntax is often annoying.

That's a somewhat complicated example, where they have a multiplier (with register) operating at full-speed being shared by two half-speed paths.

But again, it comes down to the same: the logic in that examples guarantees that the multiplier register launches data 2 clock cycles before an output register latches it.

Note that ab_out latches when div_by_two is '0', while xy_out latches when div_by_two is '1'.

It also, somewhat, assumes that the same is true for the inputs latched by the input registers.