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Honored Contributor
Honored ContributorHow to set multicycle for this design?
In my design, all clocks are clka (100 MHz), but clock enables are used to make registers change at 25 MHz or 6.25 MHz. The signal path is reg1(clka,100MHz)->reg2(enable to 25 MHz, clocked by cl...
Altera_ForumHonored Contributor
Honored ContributorTry to put your signal names between "".
TCL syntax is often annoying. That's a somewhat complicated example, where they have a multiplier (with register) operating at full-speed being shared by two half-speed paths. But again, it comes down to the same: the logic in that examples guarantees that the multiplier register launches data 2 clock cycles before an output register latches it. Note that ab_out latches when div_by_two is '0', while xy_out latches when div_by_two is '1'. It also, somewhat, assumes that the same is true for the inputs latched by the input registers.
