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14 years agoHow to receive LVDS ADC data
Hi,
My design is still using cyclon I, EP1C4F324C6. It will connect to a serial output A/D conveter which has four lines (represent four channel outputs) and one frame line and one clock line. All lines are LVDS ones. The channel bit rate is 280Mb/s and the frame (it has 14 bits) cycle is 50ns but clock frequency is 140MHz. Both its rising edge and falling edge indicate the data content. How to design the FPGA to receive the serial data? Should i use LVDS transceiver IP? But,I do not have any extra PLL. Or, is there any other way? I tried to use gate logic to receive it directly but it failed at the frame cycle less than 140ns(upto 7Mhz). The problem is i need a globle clock over 560MHz. It looks like impossible for Cyclon I. I am a beginer. Any helps and suggestions are very appreciated!