Forum Discussion
9 Replies
- Altera_Forum
Honored Contributor
--- Quote Start --- i want to realize demodulation module in EP2C35 with verilog code,the frequency of carrier wave is 10KHz, and the frequency of modulation wave is 2.5MHz. what method or algorithm is suitable? --- Quote End --- What is the modulation format of the data you are trying to analyze; is it an analog modulation scheme (AM, FM), or digital modulation scheme? The term modulation is sometimes used to mean frequency shift up and down. In that case, demodulation consists of multiplication of the input signal with a cosine and sine waveform; mathematically, this is a complex exponential. Please take a look at these documents; http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf) What is the signal you are trying to receive? Regards, Dave - Altera_Forum
Honored Contributor
The signal flow is as following:
analog signal from Ultrosonic Probe -> A/D -> FPGA(using digital demodulation shceme) Generally,Hillbert convert is used to demodulation,but it is difficult to be realized in FPGA,i think.So I am searching other ways which are not so difficult. Thank you Dave for the material you provided. - Altera_Forum
Honored Contributor
--- Quote Start --- The signal flow is as following: analog signal from Ultrosonic Probe -> A/D -> FPGA(using digital demodulation shceme) Generally,Hillbert convert is used to demodulation,but it is difficult to be realized in FPGA,i think.So I am searching other ways which are not so difficult. --- Quote End --- Ok, so your signal is analog. Just to be clear; your ultrasonic signal has 10kHz bandwidth on a 2.5MHz carrier? Are you transmitting and receiving the signal, i.e., is this an active ultrsonic system? Do you need to pulse compress the received signal, eg., if the transmit signal is a linear FM chirp. Do you have an array of receivers, or just one? Hilbert transforms can be used to convert a real-valued signal to a complex-valued (analytic) signal. However, demodulation to baseband followed by filtering and decimation achieves much the same thing, but the filters are symmetric, so the response is better. What is your ADC sample rate? If you are sampling DC to ~2.5MHz, I would expect something higher than 2.5MHz, but if you are bandpass filtering your 2.5MHz signal, you could sub-sample and digitally alias the signal. What are you planning on doing? Cheers, Dave - Altera_Forum
Honored Contributor
yes,my ultrosonic signal has 10KHz bandwidth on a 2.5MHz carrier,and I just receive echo signal and process it.In my system there are 30 ultrosonic transceivers,but the process flow of each one is the same.
The sample rate of A/D is 30MSPS to the echo signal. Up to now,I have no good idea,maybe a low pass filter is ok, but I don't try it yet.Someone think DQD(digital quadrature detection) is useful. I have no idea what way is the best for my project. - Altera_Forum
Honored Contributor
--- Quote Start --- yes,my ultrosonic signal has 10KHz bandwidth on a 2.5MHz carrier,and I just receive echo signal and process it.In my system there are 30 ultrosonic transceivers,but the process flow of each one is the same. The sample rate of A/D is 30MSPS to the echo signal. Up to now,I have no good idea,maybe a low pass filter is ok, but I don't try it yet.Someone think DQD(digital quadrature detection) is useful. I have no idea what way is the best for my project. --- Quote End --- The most efficient solution will be to use digital demodulation to complex-valued baseband and then decimate the data using a cascade of CIC filters, half-band filters, and a band shaping FIR filter. Since your sampling rate is slower than the FPGA clock rate, which could be 3x (90MHz) to 10x (300MHz) faster than the ADC rate, you can probably re-use FPGA logic via time-division multiplexing (also known as folding). --- Quote Start --- process flow of each one is the same. --- Quote End --- Are you sure its exactly the same? Most ultrasonic arrays implement beam-forming, and in that case, each signal would be independently delayed and summed to form beams (multiple beams require different per sensor delays). Cheers, Dave - Altera_Forum
Honored Contributor
--- Quote Start --- The most efficient solution will be to use digital demodulation to complex-valued baseband and then decimate the data using a cascade of CIC filters, half-band filters, and a band shaping FIR filter. Since your sampling rate is slower than the FPGA clock rate, which could be 3x (90MHz) to 10x (300MHz) faster than the ADC rate, you can probably re-use FPGA logic via time-division multiplexing (also known as folding). --- Quote End --- Firstly,thank you every much for your advise.I will find materials about how to realize it in FPGA logic. --- Quote Start --- Are you sure its exactly the same? Most ultrasonic arrays implement beam-forming, and in that case, each signal would be independently delayed and summed to form beams (multiple beams require different per sensor delays). --- Quote End --- My system isn't used in medical instruments or like that,so it's different with what you said.Each ultrasonic channel is independent from others.The process flow of each ultrasonic channel is similar,and the difference is the parameters which used in process module. - Altera_Forum
Honored Contributor
--- Quote Start --- Firstly,thank you every much for your advise.I will find materials about how to realize it in FPGA logic. --- Quote End --- The link to the paper I sent you earlier in this discussion has plenty of references. --- Quote Start --- My system isn't used in medical instruments or like that,so it's different with what you said.Each ultrasonic channel is independent from others.The process flow of each ultrasonic channel is similar,and the difference is the parameters which used in process module. --- Quote End --- Ok, thanks. Are you generating the 10kHz signal on the 2.5MHz carrier? If so, it will make your system design easier if the FPGA processing the receiver channels uses the same reference frequency as the transmitter. Out of interest, why is the ultrasonic bandwidth only 10kHz? That seems like a very narrow bandwidth (relative to the sonar and medical ultrasound devices I've used). Cheers, Dave - Altera_Forum
Honored Contributor
--- Quote Start --- Are you generating the 10kHz signal on the 2.5MHz carrier? If so, it will make your system design easier if the FPGA processing the receiver channels uses the same reference frequency as the transmitter. Out of interest, why is the ultrasonic bandwidth only 10kHz? That seems like a very narrow bandwidth (relative to the sonar and medical ultrasound devices I've used). --- Quote End --- Maybe I didn't express clearly. 10KHz isn't the bandwith of ultrasonic signal,which is the frequency of envelope of modulated signal. - Altera_Forum
Honored Contributor
--- Quote Start --- Maybe I didn't express clearly. 10KHz isn't the bandwith of ultrasonic signal,which is the frequency of envelope of modulated signal. --- Quote End --- That is still not clear to me. Can you describe how you are generating the ultrasonic pulse. Are you amplitude modulating a 2.5MHz signal with a 10kHz sinusoid? Is this continuous, or pulsed? If its pulsed, what is the pulse length? Is your hardware responsible for generating the transmit signal and the received signal? If you are, then this will make the system design easier, since the 2.5MHz carrier will be in common. If you do not control the transmitter, then can you use a common reference, so that your transmitter and receiver can generate 2.5MHz references relative to the same reference? Cheers, Dave