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The most efficient solution will be to use digital demodulation to complex-valued baseband and then decimate the data using a cascade of CIC filters, half-band filters, and a band shaping FIR filter. Since your sampling rate is slower than the FPGA clock rate, which could be 3x (90MHz) to 10x (300MHz) faster than the ADC rate, you can probably re-use FPGA logic via time-division multiplexing (also known as folding).
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Firstly,thank you every much for your advise.I will find materials about how to realize it in FPGA logic.
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Are you sure its exactly the same? Most ultrasonic arrays implement beam-forming, and in that case, each signal would be independently delayed and summed to form beams (multiple beams require different per sensor delays).
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My system isn't used in medical instruments or like that,so it's different with what you said.Each ultrasonic channel is independent from others.The process flow of each ultrasonic channel is similar,and the difference is the parameters which used in process module.
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