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Honored Contributor
Honored ContributorHow to make a NULL FPGA (CycloneII) - a complete empty design
I am trying to make a FPGA design that behaves just like an unconfigured FPGA - from a boundary scan point of view.
Why ? we test boards with Boundary scan ,and factory new boards with empty flash are never a problem,the FPGA is unconfigured and finds no valid code to configure. If we want to retest a board from the field,it comes with a programmed flash,and starts up immediately after power up.The active content of the FPGA (generally a NIOSII plus something) interferes with the boundary scan functionality. I can use the JTAG tools to reprogram the FPGA with something else (blow in a SVF file) that works fine,kills the NIOS,but afterwards the boundary scan cells are not behaving the same as with an unconfigured device. In MAXII devices it works to make a design with all inputs (as many as the device has User I/O's) but now with a Cyclone II this trick doesnot work. I made a design like this : ------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity EP2C5Q208_null is port ( signal GENIO : INOUT STD_LOGIC_VECTOR(131 downto 1); signal GENIN : IN STD_LOGIC_VECTOR(8 downto 1) ); end entity EP2C5Q208_null; architecture RTL of EP2C5Q208_null is begin end RTL; ------------------------------------------------------------------- and even used the BSDL customizer,and tried to test the design with a modified BSDL file,but nothing seems to work. If you read Altera's AN039 document,it describes the boundary scan cell integration in the IO's but doesnot mention what heppens after configuration.
