Honored Contributor
Honored ContributorWell guys,thanks for thinking along with me.
I am a little further now. 1) assigning th pins to Z doesnot work.The pin file shows 'bidir' for the pins but if you go to the "chip planner" in Quartus,you'll see that the Output Enable is not connected. Quartus is too smart in this,whwnever it can it will optimize,an if it sees that the output is always or never enabeled,it will not even connect the output enable. The following design works: entity EP2C5Q208_null is port ( signal GENIO : INOUT STD_LOGIC_VECTOR(131 downto 1); signal GENIN : IN STD_LOGIC_VECTOR(7 downto 1); signal TS : IN STD_LOGIC ); end entity EP2C5Q208_null; architecture RTL of EP2C5Q208_null is begin process(TS) begin if TS='0' then GENIO <= "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; end if; if TS='1' then GENIO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; end if; end process; -------------------------------------------------------------------------- I can do boundary scan tests on it just like it were an empty chip (except for the TS line ofcoarse).The IO cells all have 3 connections if you look in the "chip planner" and click on some IO cell.I don't even need de BSDL customizer. 2)RUBIKIAN, to answer your thread : it just doesnot do what I expect. I think (now) that its main purpose is removing the LVDS assignments from being scannable.The cause of the boundary scan not testing correct lies in the fact that I/O cells must have 3 connections (DATAIN,OE and COMBOUT) in a configured device. At first I thought that unconfigured,or unused pins were removed from the scan chain in a configured device,rendering a shorter chain.But this is not the case.The scan cells are only changed in their behaviour,and the scan chain always has the same length,device being configured or not.
