How to make a NULL FPGA (CycloneII) - a complete empty design

May be the pins are driving out, cause you set them to inout without setting 'Z' output state. I did'nt understand, why you defined the port pins at all. They aren't needed for a blank design.

I have e. g. a blank SFL design, it uses no port pins (apart from internal defined ASMI pins). In this case, the ununsed pins setting has to be input tristated or similar. But I think, you could also force outputs in BSDL, so I don't actually understand, how BSDL functionality can be blocked by a configuration