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Honored Contributor
Honored ContributorHow to make a NULL FPGA (CycloneII) - a complete empty design
I am trying to make a FPGA design that behaves just like an unconfigured FPGA - from a boundary scan point of view. Why ? we test boards with Boundary scan ,and factory new boards with empty flash...
Altera_ForumHonored Contributor
Honored ContributorWell it looks like the JTAG capture function isn't working properly.
I have 18 test vektors,and the readback from vektor 2...17 is the same as of vektor 1. It should however read only 1 difference :the state of the nCONFIG pin.
