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Honored Contributor
Honored ContributorHow to make a NULL FPGA (CycloneII) - a complete empty design
I am trying to make a FPGA design that behaves just like an unconfigured FPGA - from a boundary scan point of view. Why ? we test boards with Boundary scan ,and factory new boards with empty flash...
Altera_ForumHonored Contributor
Honored ContributorYes, the scanchain is hardware wired and that is why it is not changed in length.
For LVDS, the N-pin is not connected to the IO pin while in Boundary Scan mode. The P-pin will behave like the usual IO pin. Therefore, you have to set the N-pin as untestable in the BSDL file by making it linkage pin and setting the behavior to untestable.
