How to let FPGA get access to HPS pins

Thanks Marcopoliptica.

After hours of trying all these different multiplexing options I have got it working ;)

I used to Pin Assignments window to identify the correct GPIO routing for the UART/USB external connector (PIN_B25 and PIN_C25). Both of these are NOT on the loan 61 and 62 but in fact 49 and 50! ... so I used the same LOANIO method and exported 49 and 50 which worked and the fitter assigned them to the desired pins.

61 and 62 would always (correctly) get fitted to PIN_B22 and PIN_G22 respectively, but of course the external connector is physically routed to the above pins.

Thanks again for your help,

I can now use the external UART/USB with my softcore processor ;)

RE the voltage error, yes I later realised I just change them from '2.5 V (default)' to '3.3-V LVTTL' and it compiles.

Hi Dez74,

If you want to use LOANIO61/LOANIO62 for UART0, you can set the "UART0 pin multiplexing" to "HPS I/O Set 1" in QSys instead of routing it to the FPGA. Then you can just route to I/O ports in the top file, and during compilation it will automatically set those pins to B25 and C25.

As for the error (169026), this is due to the HPS_UART_RX/TX pins being set to 3.3V, while the bank is at 2.5V. In the pin planner, set the I/O Standard of these pins to 2.5V.

Marcopoliptica

Hi davidc85,

I am trying to export the UART0 from the DE1-SoC board to the FPGA but I am unable to determine how to assign the "top level" ports.. ??

As was mentioned, you get the ports for the hps component.. for the UART0 they are as follows in my top level verilog code:

// loanio uart0

.hps_0_hps_io_hps_io_gpio_inst_LOANIO61 (<connect to top level>),

.hps_0_hps_io_hps_io_gpio_inst_LOANIO62 (<connect to top level>),

//

So, I am assuming these need to be assigned to the board pins:

"HPS_UART_RX (pin_b25)" and "HPS_UART_TX (pin_c25)" respectively

My question is how you did this? .. in the pin assignents you can't choose these pins as they are reserved?

When I compile the project I get the error (for pins B25 and C25):

Error (169026): Pin HPS_UART_RX is incompatible with I/O bank 7A. It uses I/O standard 2.5 V, which has VCCIO requirement of 2.5V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 3.3V.

Error (169026): Pin HPS_UART_TX is incompatible with I/O bank 7A. It uses I/O standard 2.5 V, which has VCCIO requirement of 2.5V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 3.3V.

Any help is appreciated, thanks in advance. I have searched and looked for solutions here and this thread was the closest I could find and your reply above mentioned you managed to get this compiled.

other details...

Using Quartus etc version 14.0

I know how to make the preloader and linux SD Card.

You would need to boot from either QSPI or an SD card to get the HPS going.

SD Card: http://www.rocketboards.org/foswiki/documentation/gsrdsdcard

QSPI: http://www.rocketboards.org/foswiki/documentation/gsrdqspiboot

http://www.rocketboards.org/foswiki/documentation/gsrdqspiprogram

You do need to enable QSPI in Qsys, otherwise it will not work. Also, if you use the ByteBlaster on the JTAG, you can program the QSPI within the embedded command shell (steps 6 and 7 here: http://www.rocketboards.org/foswiki/documentation/gsrdqspiprogram). However, I've found using the SD card is a bit easier to start.

Which board are you using? Is it a custom board? The RocketBoards.org site has some pretty good examples on getting some of the dev boards going.

--- Quote Start ---

You should be able to loan the HPS pins to the FPGA.

Go to the Hard Processor Configuration page in your Qsys module. In the 'Peripheral Pin Multiplexing' tab, there is a Peripherals Mux Table at the bottom. There you can select HPS pins to act either as a GPIO or be loaned to the FPGA. Click on the LoanIO buttons of the UART pins. Don't forget to disable the corresponding UART controller, or else it will complain about conflicts. Click 'Finish'.

Back in the Qsys project, the HPS entry should now have a new 'h2f_loan_io' conduit. Double-click to export the signals. Re-generate the system. If you look at the HDL example, you'll notice a few new signals. For example, if I loaned IO20:

.hps_io_hps_io_gpio_inst_LOANIO20 <-- Connect to top level inout pin

.loan_io_in <-- Connect to FPGA logic

.loan_io_out <-- Connect to FPGA logic

.loan_io_oe <-- Connect to FPGA logic

All of the "loan_io_x" signals are the size of the maximum IO pins. For example, the Cyclone V these are [66:0].

The loan_io_oe controls whether the pin is an output. If '1' at the specified location (in this case loan_io_oe[20] = 1'b1), then it is an output, and you can control the pin writing to loan_io_out[20].

To read an input to the FPGA, just read loan_io_in[20], and set loan_io_oe[20] to 0.

Hope this helps.

--- Quote End ---

Thanks for your reply. This is very helpful, but I still have a couple of questions if you don't mind.

I've made the Qsys system which only has the HPS module and I've exported all HPS ports. This way I can instantiate the HPS in my VHDL code and connect all I/O's, clock and reset myself. I've then succesfully built the whole design, but my question is now, how do I program the HPS such that it gets configured with the Qsys configuration that I made?

I can see that there is a "handoff" folder which should contain the files needed to make a new BSP. I made the BSP and got a preloader bin file, but I'm not sure what to do from here?! Can I program the HPS directly or do I need to program either the QSPI or put the BIN on a SD card and use bootsel to select either one?

If I need to e.g. program the QSPI and use bootsel to select that the HPS needs to boot from QSPI, do I then need to have enabled QSPI inside the HPS in Qsys and mapped the I/O pins ?? And how do I actually program the QSPI? Is there a tool like the Quartus Programmer or some CLI command?

Thanks :-)

You should be able to loan the HPS pins to the FPGA.

Go to the Hard Processor Configuration page in your Qsys module. In the 'Peripheral Pin Multiplexing' tab, there is a Peripherals Mux Table at the bottom. There you can select HPS pins to act either as a GPIO or be loaned to the FPGA. Click on the LoanIO buttons of the UART pins. Don't forget to disable the corresponding UART controller, or else it will complain about conflicts. Click 'Finish'.

Back in the Qsys project, the HPS entry should now have a new 'h2f_loan_io' conduit. Double-click to export the signals. Re-generate the system. If you look at the HDL example, you'll notice a few new signals. For example, if I loaned IO20:

.hps_io_hps_io_gpio_inst_LOANIO20 <-- Connect to top level inout pin

.loan_io_in <-- Connect to FPGA logic

.loan_io_out <-- Connect to FPGA logic

.loan_io_oe <-- Connect to FPGA logic

All of the "loan_io_x" signals are the size of the maximum IO pins. For example, the Cyclone V these are [66:0].

The loan_io_oe controls whether the pin is an output. If '1' at the specified location (in this case loan_io_oe[20] = 1'b1), then it is an output, and you can control the pin writing to loan_io_out[20].

To read an input to the FPGA, just read loan_io_in[20], and set loan_io_oe[20] to 0.

Hope this helps.