How to let FPGA get access to HPS pins

You should be able to loan the HPS pins to the FPGA.

Go to the Hard Processor Configuration page in your Qsys module. In the 'Peripheral Pin Multiplexing' tab, there is a Peripherals Mux Table at the bottom. There you can select HPS pins to act either as a GPIO or be loaned to the FPGA. Click on the LoanIO buttons of the UART pins. Don't forget to disable the corresponding UART controller, or else it will complain about conflicts. Click 'Finish'.

Back in the Qsys project, the HPS entry should now have a new 'h2f_loan_io' conduit. Double-click to export the signals. Re-generate the system. If you look at the HDL example, you'll notice a few new signals. For example, if I loaned IO20:

.hps_io_hps_io_gpio_inst_LOANIO20 <-- Connect to top level inout pin

.loan_io_in <-- Connect to FPGA logic

.loan_io_out <-- Connect to FPGA logic

.loan_io_oe <-- Connect to FPGA logic

All of the "loan_io_x" signals are the size of the maximum IO pins. For example, the Cyclone V these are [66:0].

The loan_io_oe controls whether the pin is an output. If '1' at the specified location (in this case loan_io_oe[20] = 1'b1), then it is an output, and you can control the pin writing to loan_io_out[20].

To read an input to the FPGA, just read loan_io_in[20], and set loan_io_oe[20] to 0.

Hope this helps.